1. Field of the Invention
This invention relates to a method of and an apparatus for placement, upon designing of an integrated circuit (LSI, VLSI, ASIC or the like) having a plurality of routing layers of, for example, the gate array, of cells on a chip in a situation wherein a wire has already routed prior to such placement of cells such as a bulk power supply or a clock signal are present as well as a storage medium on which a cell placement program is stored.
2. Description of the Related Art
As a most representative one of integrated circuits such as, for example, application specific integrated circuits (ASICs), a gate array of the full area device type having no region for exclusive use for routing is known. In order to produce a gate array, a master wafer for which a step of production of transistors has completed and in which basic cells each formed from a plurality of transistors are placed in gratings is prepared in advance, and the connection of routing of a metal is changed so as to realize a desired. function.
A gate array produced in this manner usually has a plurality of routing layers (for example, three layers), and a wire such as a bulk power supply or clock a signal is sometimes routed already on some of those layers prior to placement of cells. FIG. 13 shows in plan view an example wherein bulk power supply wires (Vdd and Vss) 1 are routed already. Further, an enlarged view of a XIV portion in FIG. 13 is shown in FIG. 14. It is to be noted that the size of one grating shown in FIG. 14 corresponds to the size of a basic cell, and such grating is hereinafter referred to as site unit. Cells are placed along frames of site units without fail. If a grating frame along which cells are placed is used as a unit, the cells need not be basic cells.
If a cell 2 is placed, in a situation wherein a bulk power supply wire (already routed wire) 1 is present, at a position at which it overlaps with the bulk power supply wire 1 as viewed on the plane of the chip as seen in FIG. 14, if a wiring pattern 3 in the cell 2 and the bulk power supply wire 1 are present in the same routing layer, then they short-circuit to each other.
Therefore, in order to prevent occurrence of such short-circuiting with certainty, it is a conventional countermeasure to produce a cell placement prohibition in advance in a region decided to be passed by any bulk power supply wire 1 so that, when automatic placement of cells 2 is to be performed subsequently, the cells 2 may not be placed in the region at all.
Accordingly, with such a conventional cell placement procedure as described above, even if the routing layer of a bulk power supply wire 1 and the routing layer of the wiring pattern 3 in a cell 2 are different from each other and no short-circuiting actually occurs between them, it is quite impossible to place the cell 2 at a position at which it overlaps with the bulk power supply wire 1 as viewed on the plane of the chip.
In short, since placement of a cell 2 in a region (already routed region such as a bulk power supply wire 1) in which it is actually possible to place a cell 2 is prohibited completely, the area which can be used for placement of cells 2 is remarkably smaller than the actual size of a base bulk.
In designing of an integrated circuit such as an LSI, a VLSI or an ASIC, it is necessary to place cells and route between them within a limited area so that specifications or electric characteristics of a circuit may be satisfied. Particularly in recent years, an increase in density and function is required, and it is important that cells are placed efficiently on a single chip.
Thus, it is desired that placement of a cell 2 in a region in which a cell 2 can be placed be not prohibited and the region be utilized effectively so as to place cells as many as possible.